Adding FIFO tracing capabilities in simulation.#1592
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…o:bool = True however not quite there yet for the rtlsim.@
…es, this was causing issues during verify rtlsim where multiple SV modules were trying to fopen the same logfile simultaneously.
…ta to stderr instead of to individual logfiles. Also cleaner shutdown of RTL sim with exposed external sim port that calls in an always_ff block, this now enables the printing of transaction counts in the debug fifo when simulation terminates.
…ctually being written
…hat final block workaround is working.
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Improving debug capabilities by fifo_gauge and improved behavioral simulation support for verification.
What is in this PR:
sim_finish.DATA_LOGFILE.